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CYCLE_4 generates theStates 0..3 if E = TRUE . The duration of each State can be determined by the time constraints T0..T3. The input SL starts when TRUE from a predetermined STATE SX. The input E has the internal Default = TRUE, so that it can also be left open. After a rising edge on E the module always starts with STATE = 0, and if E = FALSE, the output STATE remains at 0. With the input of S0 the cyclic mode is turned on, if S0 = FALSE the module stops at State = 3, if S0 = TRUE, the device begins to State 3 again with State 0. |